Multiplication logic circuit

ABSTRACT

A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

[0001] The present invention generally relates to digital electronicdevices and more particularly to a multiplication logic circuit formultiplying two binary numbers and a multiply-accumulate logic circuitfor multiplying and accumulating previous multiplications.

[0002] It is instrumental for many applications to have a block thatadds n inputs together. An output of this block is a binaryrepresentation of the number of high inputs. Such blocks, calledparallel counters (L. Dadda, Some Schemes for Parallel Multipliers, AltaFreq 34: 349-356 (1965); E. E. Swartlander Jr., Parallel Counters, IEEETrans. Comput C-22: 1021-1024 (1973)), are used in circuits performingbinary multiplication. There are other applications of a parallelcounter, for instance, majority-voting decoders or RSA encoders anddecoders. It is important to have an implementation of a parallelcounter that achieves a maximal speed. It is known to use parallelcounters in multiplication (L. Dadda, On Parallel Digital Multipliers,Alta Freq 45: 574-580 (1976)).

[0003] A full adder is a special parallel counter with a three-bit inputand a two-bit output. A current implementation of higher parallelcounters i.e. with a bigger number of inputs is based on using fulladders (C. C. Foster and F. D. Stockton, Counting Responders in anAssociative Memory, IEEE Trans. Comput C-20: 1580-1583 (1971)). Ingeneral, the least significant bit of an output is the fastest bit toproduce in such implementation while other bits are usually slower.

[0004] The following notation is used for logical operations:

[0005] ⊕-Exclusive OR;

[0006]

-OR;

[0007]

-AND;

[0008]

-NOT.

[0009] An efficient prior art design (Foster and Stockton) of a parallelcounter uses full adders. A full adder, denoted FA, is a three-bit inputparallel counter shown in FIG. 1. It has three inputs X₁, X₂, X₃, andtwo outputs S and C. Logical expressions for outputs are

S=X₁⊕X₂⊕X₃,

C=(X₁

X₂)

(X₁

X₃)

(X₂

X₃).

[0010] A half adder, denoted HA, is a two bit input parallel countershown in FIG. 1. It has two inputs X₁, X₂ and two outputs S and C.Logical expressions for outputs are

S=X₁ 61 X₂,

C=X₁

X₂.

[0011] A prior art implementation of a seven-bit input parallel counterillustrated in FIG. 2.

[0012] Multiplication is a fundamental operation Given two n-digitbinary numbers

A _(n-1)2^(n-1) +A _(n-2)2^(n-2) + . . . +A ₁2+A ₀ and B _(n-1)2^(n-1)+B _(n-2)2^(n-2) + . . . +B ₁2+B ₀,

[0013] their product

P _(2n-1)2^(2n-1) +P _(2n-2)2^(2n-2) + . . . +P ₁2+P ₀

[0014] may have up to 2n digits. Wallace has invented the firstarchitecture for a multiplier, now called the Wallace-tree multiplier(Wallace, C. S., A Suggestion for a Fast Multiplier, IEEE Trans.Electron. Comput. EC-13: 14-17 (1964)). Dadda has investigated bitbehaviour in a multiplier (L. Dadda, Some Schemes for ParallelMultipliers, Alta Freq 34: 349-356 (1965)). He has constructed a varietyof multipliers and most multipliers follow Dadda's scheme.

[0015] Dadda's multiplier uses the scheme in on FIG. 3. If inputs have 8bits then 64 parallel AND gates generate an array shown in fig=re 4. TheAND gate sign

is omitted for clarity so that A_(i)

B_(j) becomes A_(i)B_(j). The rest of FIG. 4 illustrates array reductionthat involves full adders (FA) and half adders (HA). Bits from the samecolumn are added by half adders or full adders. Some groups of bits fedinto a full adder are in rectangles. Some groups of bits fed into a halfadder are in ovals. The result of array reduction is just two binarynumbers to be added at the last step. One adds these two numbers by oneof the fast addition schemes, for instance, conditional adder orcarry-look-ahead adder.

[0016] UK patent application numbers 0019287.2 and 0101961.1, U.S.patent application Ser. Nos. 09/637,532, 09/759,954 and 09/917,257 andInternational patent application numbers GB01/03415 and GB01/04455, thecontents of all of which are hereby incorporated by reference, disclosea technique for the modification or deformation of the array prior toarray reduction. The array deformation derives the benefit of reducingthe depth of the array to a number greater than 2^(n-1)−1 and less thanor equal to 2^(n)−1, where n is an integer. This reduction of themaximum depth of the array enables the efficient use of parallelcounters in the array reduction step.

[0017] It is an object of the present invention to provide an improvedmultiplication logic circuit and an improved multiply-accumulate logiccircuit in which the speed of operation of the logic circuit isimproved.

[0018] The present inventors have realised that in the array reductionstep the use of maximal length parallel counters can significantlyreduce wiring delays present in the prior art array reduction logic. Theinventors have also however realised that the outputs of the maximumlength parallel counters experience different gate delays. Thus inaccordance with the present invention, in addition to the use of maximallength parallel counters in the array reduction step, the outputs of themaximal length parallel counters are input to reduction logic circuitswith asymmetric delays to ameliorate the effects of the differentialdelays of the output of the parallel counter circuits.

[0019] Thus in accordance with the present invention, outputs generatedfrom the maximal length parallel counter logic that experience shorterdelays are input to reduction logic inputs which incur longer delays inthe generation of the output Outputs of the maximal length parallelcounter logic that experiences longer delays with the parallel counterlogic are input to inputs of the asymmetric reduction logic whichexperience shorter delays in the generation of the output. Thus in thisway the overall delays through the parallel counter logic and thefurther reduction logic are balanced and the differences in delaysthrough the parallel counter logic is compensated for by the furtherreduction logic.

[0020] In accordance with the present invention, at least one maximalparallel counter is used in the array reduction step to reduce the arrayin one dimension by receiving all of the values in the array in onecolumn

[0021] In a preferred embodiment of the present invention the array ismodified by undergoing the array deformation as disclosed in copendingUK applications numbers 0019287.2 and 0101961.1, U.S. patent applicationSer. Nos. 09/637,532, 09/759,954 and 09/917,257 and International patentapplication numbers GB01/03415 and GB01/04455. Array deformationprovides the benefit of reducing the number of inputs for a maximalcolumn to a number greater than 2^(n-1)−1 and less than or equal to2^(n)−1, where n is an integer. For example, for the multiplication oftwo 16 bit numbers, the array deformation process reduces the maximaldepth of the array to 15 bits in any given column thereby enabling 15bit input, 4 bit output parallel counters to be used in the firstreduction step to reduce the array depth to a maximum of 4 bits. For a32 bit input, the array deformation step reduces the maximal height ofthe array to 31 bits in any given column thereby enabling a 31 bitinput, 5 output parallel counter to be used to provide an array ofreduced depth which is a maximum of 5 bits.

[0022] In an embodiment of the present invention, the reduction logicwith asymmetric delays comprises any combination of fill adders, halfadders and 4 to 2 compressors. Where a number of outputs from theparallel counters is 4 or more, 4 to 2 compressors are preferably usedto generate to 2 bit outputs.

[0023] Embodiments of the present invention will now be described withreference to the accompanying drawings, in which.

[0024]FIG. 1 is a schematic diagram of a full adder and a half adder inaccordance with the prior art.

[0025]FIG. 2 is a schematic diagram of a parallel counter using fulladders in accordance with the prior art;

[0026]FIG. 3 is a diagram of the steps used in the prior art formultiplication;

[0027]FIG. 4 is a schematic diagram of the process of FIG. 3 in moredetail;

[0028]FIG. 5 is a schematic diagram illustrating the structure of agenerated deformed array in accordance with an embodiment of the presentinvention;

[0029]FIG. 6 is a schematic diagram illustrating the array afterreduction by maximal length parallel counters in accordance with anembodiment of the present invention;

[0030]FIG. 7 is a diagram of the logic of a full adder showing the gatedelays;

[0031]FIG. 8 is a schematic diagram of a 4 to 2 compressor constructedfrom full adders in accordance with an embodiment of the presentinvention;

[0032]FIG. 9 is a schematic diagram of the logic circuit for the secondstage of the array reduction using 4 to 2 compressors in accordance withan embodiment of the present invention; and

[0033]FIG. 10 is a diagram of the logic of a 4 to 2 compressor.

[0034] In the embodiment illustrated in FIG. 5, the array generated inthe process for multiplying two 16 bit binary numbers A and B is formedas a deformed array in accordance with the process disclosed incopending UK patent applications numbers 0019287.2 and 0101961.1, U.S.patent application Ser. Nos. 09/637,532, 09759,954 and 09/917,257 andInternational patent application numbers GB01/03415 and GB01/04455, thecontents of which are hereby incorporated by reference. The advantage ofthis array over the array of the prior art as illustrated in FIG. 4 isthat the maximum number of bits in a column is smaller. In the priorart, for a 16 bit multiplication, a column will have 16 bits. The arrayof FIG. 5 has four columns with 15 bits.

[0035] The first reduction step to reduce the array comprises the use ofparallel counters to reduce each column from a maximum of 15 bits to 4bits maximum as illustrated in FIG. 6. Any conventional parallelcounters can be used for reducing the maximal columns of 15 bits to 4bits, although it is preferable to use the parallel counters disclosedin the copending applications identified above.

[0036] The 4 bits output from the parallel counters will haveexperienced different gate delays. Typically 2 outputs experience 4 gatedelays and 2 outputs experience 5 gate delays. However, the use of asingle logic circuit in the form of a maximal length parallel counterfor the reduction of the array greatly reduces the wiring betweencircuits. There is thus a significant wiring benefit in using maximallength parallel counters.

[0037]FIG. 7 is a logic diagram of a full adder that illustrates theasymmetric nature of the circuit. Inputs A and B can comprise outputsfrom a maximal length parallel counter which have experience 4 gatedelays and are therefore relatively advanced compared to the input tothe circuit C which is an output from the maximal length parallelcounter which has experienced 5 gate delays. Each gate delay in thisexample is expressed as an EXOR gate delay which is the slowest gate.And and OR gates are considered to have a relative delay of 0.5. FIG. 7illustrates the cumulate gate delay and as can be seen, the sum S isoutput with a cumulative gate delay of 6 and a carry C is also outputwith a cumulative gate delay of 6. Thus the fill adder can be used aspart of the second level of array reduction in order to compensate forthe relative gate delays of the outputs of the maximal length parallelcounters in the first level of array reduction.

[0038]FIG. 8 is a schematic logic diagram of two adjacent 4 to 2compressors each comprised of 2 full adders. The relative gate delaysare illustrated to illustrate the asymmetric nature of the logic used asa second level of logic reduction in this embodiment of the presentinvention.

[0039]FIG. 9 illustrates a chain of 4 to 2 compressors used to receiveeach of 4 columns of bits from the reduced array following the firstlevel of reduction by the maximal length parallel counters. The outputof the 4 to 2 compressors for each column comprises 2 bits. The 2 bitscan then be added using conventional addition logic circuitry togenerate the output binary number comprising a multiplication of the 2 nbit binary numbers.

[0040]FIG. 10 is a logic diagram of the 4 to 2 compressor in accordancewith an embodiment of the present invention.

[0041] Thus in this embodiment of the present invention an array isgenerated and modified by array deformation in accordance with theapplicant's earlier inventive array modification technique. The array isreduced in two stages. The first stage is built upon the recognitionthat the wiring of the multiplication logic circuit can be reduced if asingle parallel counter is used for the reduction of each column of thearray. This however results in outputs which have suffered differentialgate delays. Thus the invention ameliorates this problem by using asecond level of array reduction which uses logic circuits for which theinputs experience relative differential gate delays i.e., the logiccircuit imposes asymmetric delays on the inputs. In this way therelative delays caused by the use of the maximal length parallelcounters does not cause a delay in the further reduction step.

[0042] Thus this multiplication logic circuit is highly efficient sinceit has reduced wiring and increase speed because of the balancing of thegate delays in the logic circuit.

[0043] Although the present invention has been described hereinabovewith reference to a specific embodiment, it will be apparent to askilled person in the art that modifications lie within the spirit andscope of the present invention.

[0044] For example, although the present invention has been describedhereinabove with reference to a specific example in which the array isdeformed before army reduction, the present invention is applicable tothe reduction of an undeformed array. For example, the array can begenerated using any prior art technique. Any logic gate operation forperforming a logical combination of the bits can be used to form thearray such as AND, NAND, OR or NOR gates. Further the array can begenerated by the use of Booth encoding.

[0045] In the present invention any prior art parallel counter logiccircuit can be used for the first level of the array reduction. Parallelcounters can be used for any number of the columns that need not be usedfor all columns. For example, for the columns with three bits, a fulladder can be used. It may also be desirable for some columns to use fulladders rather than the parallel counter. The number of columns reducedby the use of parallel counters is a design choice. It is howeverenvisaged that it is preferable to use parallel counters for any columnshaving more than 3 bits in the array.

[0046] In accordance with the present invention, the second arrayreduction step can be implemented by any suitable logic for which thereare differential delays experienced by the inputs in the generation ofthe outputs.

[0047] Although in the present invention any form of parallel countercan be used, in a preferred embodiment, the parallel counters disclosedin UK patent applications numbers 0019287.2 and 0101961.1, U.S. patentapplication Ser. Nos. 09/637,532, 09/759,954 and 09/917,257 andInternational patent application numbers GB01/03415 and GB01/04455 areused.

[0048] In the present invention any conventional method can be used forthe final step of addition of the two binary numbers in order togenerate the output of the multiplication logic circuit.

[0049] Although the present invention has been described with referenceto a specific multiplication logic circuit the present invention alsoapplies to any logic circuit that performs multiplication including amultiply-accumulate logic circuit (which can be viewed as a special caseof a multiplication logic circuit). In a multiply-accumulate logiccircuit the operation A×B+C is implemented where C is the accumulationof previous multiplications. The multiply-accumulate logic circuitoperates by generating the array of A×B as described hereinabove for themultiplication logic circuit. An additional row is added in the arrayfor the bits of C. C can have many more bits than A or B due to previousaccumulations. This enlarged array then undergoes array reduction asdescribed hereinabove.

[0050] The present invention encompasses any method of designing andmanufacturing the inventive multiplication logic circuit as hereinabovedescribed. The present invention further encompasses code or datacharacterizing the inventive multiplication logic circuit Also thepresent invention encompasses code for modelling the inventivefunctionality of the multiplication logic circuit as describedhereinabove.

[0051] It is well known in the field that logic circuits can be designedon computer systems using code executed to model the functionality ofthe logic circuit. The result of such a design procedure is codedefining the features and functionality of the logic. Thus, codedefining the characteristics or functions of the logic circuit can bemade available to logic designers and builders. The code for designingand the code for defining the characteristics or functions of the logiccircuit can be made available on any suitable carrier medium such as astorage medium, e.g. a floppy disk, hard disk, CD-ROM, tape device, orsolid state memory device, or a transient medium such as any type ofsignal, e.g. an electrical signal, optical signal microwave signal,acoustic signal, or magnetic signal (e.g. a signal carried over acommunications network).

[0052] A logic circuit manufacturer can thus be provided with codedefining the characteristics or functions of the standard cells and thiscode can be used for the manufacture of a logic circuit in semiconductormaterial using known manufacturing techniques.

[0053] In one embodiment of the present invention, the design processencompasses the use of standard cells using a standard cell designprocess. A designer can implement a design program in order to designstandard cells which implement either the complete logic function orparts of the multiplication logic circuit. The design process involvesdesigning, building and testing the standard cells in silicon and theformation of a library of data characterizing the standard cells whichhave been successfully tested. This library of data characterizingstandard cell designs contains information which can be used in thedesign of a logic circuit using the standard cells. The data or code inthe library thus holds characteristics for the logic circuit whichdefines a model of the standard cell. The data can include geometry,power and timing information as well as a model of the functionperformed by the standard cell. Thus a vendor of standard cell designscan make the library of standard cell code available to logic circuitdesigners to facilitate the design of logic circuits to perform specificfunctions using the functionality of the library of standard cells. Alogic circuit designer can use the library of code for standard cells ina computer modelling implementation to assemble a logic circuit, i.e.the multiplication logic circuit using the standard cell code. Thedesigner therefore implements a design application which uses the codeto build the model of the desired logic circuit The resultant datadefines the characteristics of the logic circuit, i.e. themultiplication logic circuit, in terms of a combination of standardcells. This data can thus be used by a chip manufacturer to design andbuild the chip using the model data generated by the logic circuitdesigner.

[0054] The present invention encompasses the design of standard cellsfor implementing the functions in accordance with the present invention,i.e. the generation of model data defining the characteristics ofstandard cells implementing the inventive functions. The presentinvention also encompasses the method of designing the inventivemultiplication logic circuit using the library of standard cell data,i.e. the steps of using a computer program to generate data modellingthe characteristics of the inventive multiplication logic circuit. Theinvention also encompasses the process of manufacturing themultiplication logic circuit using the design data.

[0055] Although the present invention has been described hereinabovewith reference to specific embodiments, it will be apparent to a skilledperson in the art that modifications lie within the spirit and scope ofthe present invention.

1. A multiplication logic circuit for multiplying two binary numbers,the circuit comprising: array generation logic for generating, from thetwo binary numbers, an array of binary values which are required to beadded; array reduction logic for reducing the depth of the array to twobinary numbers; and addition logic for adding the binary values of thebinary numbers; wherein the array reduction logic comprises: first arrayreduction logic comprising a plurality of binary counters, each forreceiving the binary values of all binary numbers in a respective columnof the array, and for outputting binary numbers; and second arrayreduction logic having logic imposing asymmetric delays on inputs to thelogic and for receiving the binary numbers output from the parallelcounters at the inputs and for outputting said binary numbers to saidaddition logic.
 2. A multiplication logic circuit according to claim 1,wherein said first array reduction logic includes adder logic for addingbinary values of binary numbers in respective columns.
 3. Amultiplication logic circuit according to claim 2, wherein said adderlogic comprises at least one full adder.
 4. A multiplication logiccircuit according to claim 2 or claim 3, wherein said adder logic isarranged to add binary values of binary numbers for columns in saidarray having 3 or less bits.
 5. A multiplication logic circuit accordingto any preceding claim, wherein said second array reduction logiccomprises any one of or combination of a full adder, a half adder, andfour to two compressor logic.
 6. A multiplication logic circuitaccording to any preceding claim, wherein said array generation logic isarranged to perform a logical combination between each bit in one binarynumber and each bit in the other binary number to generate the array ofbinary values as an array of logical combinations.
 7. A multiplicationlogic circuit according to claim 6, wherein said array generation logicis arranged to perform the logical AND operation between each bit in onebinary number and each bit in the other binary number to generate thearray of binary values as an array of logical AND combinations.
 8. Amultiply-accumulate logic circuit comprising the multiplication logiccircuit according to any preceding claim, wherein said array generationlogic is arranged to include an accumulation of previousmultiplications.
 9. An integrated circuit including the logic circuitaccording to any preceding claim.
 10. A digital electronic deviceincluding the logic circuit according to any preceding claim.
 11. Amethod of designing a multiplication logic circuit according to any oneof claims 1 to 7, comprising implementing a computer program to generateinformation defining characteristics of the multiplication logiccircuit.
 12. A method according to claim 11, wherein the information isgenerated as code.
 13. A carrier medium carrying computer readable codefor controlling a computer to implement the method of claim 11 or claim12.
 14. A carrier medium carrying code generated using the method ofclaim 11 or claim
 12. 15. A design system for designing a multiplicationlogic circuit according to any one of claims 1 to 7, comprising acomputer system for generating information defining characteristics ofthe multiplication logic circuit.
 16. A carrier medium carrying modedefining characteristics of the multiplication logic circuit accordingto any one of claims 1 to
 7. 17. A method of manufacturing themultiplication logic circuit according to any one of claims 1 to 7,comprising designing and building the multiplication logic circuit insemiconductor material in accordance with code defining characteristicsof the multiplication logic circuit.